Many devices common to every day life utilize complex integrated circuits. Examples include desktop computer systems, video games, vending machines, and even pay phones. These devices often include programmable digital processors embedded within their systems. The digital processors typically implement any required user interface (e.g., a menu of choices) and execute the actual electronic processing required to implement user requests (e.g., place a phone call or order a service). The more complicated and sophisticated the device, the more complex the system including the programmable digital processor.
Programmable digital processor systems operate by executing programs, or a series of instructions, stored in a memory. These programs and series of instructions are collectively referred to as software. Software is what makes the systems function and perform useful tasks. The utility of such a system often hinges upon the speed and efficiency with which the system executes the software program. Hence, it is desirable that the programmable digital processor of the system execute software programs as fast as possible. As the programmable digital processor executes a program, there may be several significant events occurring in the system's peripheral device hardware. It is often necessary to signal the programmable digital processor to respond to an external condition, even though it is currently executing a program. This signaling process is referred to as an interrupt.
Interrupts are changes in the flow of software execution not caused by the currently running program. Some other process, usually input or output related, is responsible for the change in the flow of execution. For example, a program may instruct a peripheral device coupled to the computer system to begin a data transfer and to provide an interrupt as soon as the data transfer is complete. The interrupt stops the currently executing program and transfers control to an interrupt service routine (ISR) which performs some appropriate action. When finished, the ISR returns control of the programmable digital processor to the interrupted program. The programmable digital processor subsequently restarts the interrupted program in the same state it was in when the interrupt occurred.
The need for interrupts arise from the fact that, in most cases, input and output (IO) can proceed in parallel with processor execution. On computers where the processor issues an IO instruction and then stops to wait for the IO to be completed, there is no need for an interrupt. When the IO is finished, the processor is restarted at the instruction following the IO instruction. Because the processor can generally execute many hundreds of thousands, or even millions, of instructions during the time required to complete a single IO instruction, it is very wasteful to force the processor to be idle during this time. Interrupts and interrupt subsystems allow the processor to execute the program concurrently with the IO and be signaled as soon as the IO is completed.
Prior Art FIG. 1 shows a programmable digital processor system 100 in accordance with the prior art. System 100 includes a DSP (digital signal processor) 101 coupled to a memory 102, a first peripheral device 103, and a second peripheral device 104 via a bus 107. DSP 101 includes two interrupt request inputs, INTA and INTB, which are respectively coupled to device 104 and 103 via lines 106 and 105.
As described above, system 100 functions by DSP 101 executing a program stored in memory 102. The instructions comprising the program are sequentially fetched from memory 102 via bus 107. Device 103 and device 104 provide for user input and output (e.g., device 103 accepts keypad inputs and device 104 drives a display screen). When either device 103 or device 104 requires service from DSP 101 (e.g., impending buffer overflow, ready to accept next frame of data, or the like), an interrupt request is asserted to either INTA or INTB via lines 106 or 105. DSP 101 subsequently interrupts the currently executing program and jumps to the address in memory 102 for the particular ISR for either device 103 (e.g., in the case of an assertion on INTB) or device 104 (e.g., in the case of an assertion on INTA). Where both device 103 and device 104 concurrently assert interrupt requests, DSP 101 jumps to the appropriate ISR based upon the programmable priority between INTA and INTB. For example, where DSP 101 is programmed such that INTA is of a higher priority than INTB, the ISR corresponding to INTA is executed before the ISR corresponding to INTB.
There is a problem however, in that DSP 101 (as is typical of many DSPs) has only a limited number of interrupt request inputs. This limits the number of peripheral devices able to utilize the time saving features of interrupts. Complex DSP devices often have a large number of peripherals and perform much faster when each peripheral device couples to its corresponding interrupt request input. Similarly, in order to maintain speed and responsiveness, the number of peripherals coupled to a DSP (e.g., DSP 101) is limited to the number of interrupt request inputs included in the DSP.
Thus what is required is a method and system for expanding the number of peripherals able to efficiently couple to a programmable digital processor having a limited number of interrupt request inputs. The required system should be compatible with the large number of programmable digital processors in the electronics industry. Additionally, the required system should be modular and easily expandable. The system of the present invention provides a novel solution to the above requirements.